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STALL_MASTER Operation
STALL_MASTER allows the backend to increase the number of clock cycles it is allowed from DP_START assertion
to RD_STB_IN or WR_BE_RDY assertion for DMA transfers. As described in “Simple DMA Transfer” on page 82 ,
the PCI specification requires a Master to assert IRDYN within eight clock cycles of FRAMEN, so the backend logic
must assert these inputs within eight cycles of DP_START.
When STALL_MASTER is asserted, the core will delay the assertion of FRAMEN while the backend becomes ready.
STALL_MASTER must be asserted on the clock cycle after MAST_ACTIVE becomes active, at the same time the
core asserts DP_START. The core will then assert FRAMEN two clock cycles after STALL_MASTER is deasserted
(with STALL_MODE = 0), and IRDYN will be asserted two clock cycles after RD_STB_IN is asserted. This allows
the backend to control the FRAMEN-to-IRDYN delay (see Figure 6-45 through Figure 6-47 on page 96 ).
cycle
A0 A1 A2 A3 A4 A5 A6 A7 A8
0
1
2
3
4
5
6
7
8
clk
framen
cben[3:0]
7
0
ad[31:0]
ADDR
0
1
2
3
par
devseln
irdyn
trdyn
reqn
gntn
mast_active
stall_master
dp_start
dp_done
rd_cyc
dma_bar[2:0]
rd_stb_out
rd_stb_in
mem_add[11:0]
000
004 008 00C 010 014
mem_data_in
0
1
2
3
4
5
rd_sync
Figure 6-45 · STALL_MASTER Assertion DMA Read Cycle (RD_SYNC = 0)
94
v4.0
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